Component Watch: What's Moving This Week

A lead time is not a delay. It is a forecast of how long your competitor's design freeze has to be wrong before yours can be right.

Microcontrollers (MCUs). The constraint is structural, not cyclical. Current quoted lead times: STMicroelectronics automotive MCUs at 55 weeks, Renesas 20–45 weeks, NXP 12–20 weeks. TI and Infineon price increases (effective April 1) span +15% to +85% depending on package and grade. The root cause is mature-node (40–90 nm) capacity that nobody is adding because the fab economics favor leading-edge logic and HBM.

Silicon Carbide (SiC) MOSFETs. The old "SiC oversupply" narrative is dead. ON Semi is now critically tight, and Tier-1 EV manufacturers are locking multi-year supply agreements. Critically, the bottleneck has migrated: SiC wafer (boule) growth runs near 50% utilization, but device-level packaging — sintered-silver die attach, AMB substrates, and the high-temperature qualification flow — is running near 70% and is now the real ceiling.

DRAM & Memory. TrendForce forecasts DRAM contract prices up 58–63% in Q2, following Q1's 95% surge. NAND Flash is projected up to +75%. HBM is sold out through all of 2026 — there is no spot relief coming.

Design Corner: The Return-Path Gap Problem

Every signal current returns to its source. On a PCB above 50 MHz, that return current does not spread across the whole plane — it concentrates in a narrow band directly beneath the signal trace, because that path minimizes loop inductance and therefore minimizes impedance. The return-current density falls off approximately as:

J(d) = I₀ / [π·h·(1 + (d/h)²)]

where h is the dielectric height and d is lateral distance from the trace. About 80% of the return current flows within ±3h of the trace centerline.

Now route that trace across a split in the ground plane. The return current cannot follow underneath — it must detour around the slot. That detour is a loop, and a loop is a magnetic-dipole antenna. The added loop area can inflate radiated emissions by 15–20 dB above 300 MHz, and it raises the trace's characteristic impedance discontinuity, degrading signal integrity simultaneously.

Fixes, in order of preference:

Reroute so the trace never crosses a plane split.
If a high-speed trace must cross, bridge the split with a stitching capacitor (100 nF, 0402) placed within 1 mm of the crossing point — this gives high-frequency return current an AC path across the gap.
For multiple crossings, bridge the planes with a copper tie or stitching vias where DC isolation permits.

⚠️EMI tie-in

A board-level shield over a return-path antenna is treating a self-inflicted wound. The shield attenuates the radiation, but the loop still couples into adjacent nets. Close the loop in copper first; the shield is for what physics leaves behind.

Korean Supply Chain Intel

SK hynix HBM4 yield is reported above 70%, ahead of a major competitor's estimated 55–60%. Higher HBM yield means more module-level assembly throughput — and every HBM module and its interposer-bearing accelerator board needs board-level EMI containment over the high-speed SerDes regions. Yield news upstream is shield demand news downstream.

One Thing

STMicro automotive MCU lead time: 55 weeks. Time to design, prototype, and validate a second source: also about 55 weeks. The only way to be early is to have started yesterday.

— Mike Kwak, POCONS USA