The Signal

A $50B fab is a 30-year bet against the assumption that memory will always be cheapest from Asia.

Micron's commitment to its Boise, Idaho DRAM expansion — roughly $50B, about 25% of a larger ~$200B global capex envelope — is the clearest signal yet that the industry no longer treats Asia-default memory sourcing as a given. The driver is not nationalism; it is landed-cost arithmetic. With 25% US tariffs on Korean electronics in force since March 1, 2026, and tariff authority itself now contested in the courts, the variance on imported-memory landed cost has become large enough that domestic capacity is a hedge worth $50B.

For procurement, the near-term theme is inventory posture. Enterprise buyers are paying 15–20% premiums to build DRAM buffer stock rather than risk allocation, and that premium is rational only because the alternative — a line-down on a sold-out HBM-adjacent supply base — is worse.

Supply Chain Analysis

Memory. HBM remains sold out through 2026; commodity DDR5 rose 95% in Q1 with a 58–63% Q2 forecast. The buffer-building behavior at large OEMs is the visible consequence.

Domestic expansion. Micron's Idaho fabs are real concrete, but the timeline matters: a leading-edge DRAM fab is a 3–4 year ramp. The $50B does nothing for 2026 supply. It changes the 2028+ structure.

ℹ️Why this matters for shielding

Tariff-driven reshoring changes where boards are built, and board location changes which EMC regime governs. A design moving from an Asian CM to a US CM may shift its compliance baseline toward FCC Part 15 / MIL-STD-461H rather than CISPR — different limit lines, different test distances. Confirm the target standard before the shield is tooled.

Korean Intel

Leading Korean memory makers are absorbing margin compression at the commodity end even as HBM prints record numbers. Korean memory exports to North America declined an estimated 12% quarter-over-quarter — a direct tariff-wall effect, not a demand effect; the bits are simply being routed to non-tariff destinations.

Technical Corner

HBM4E controllers. Next-generation HBM4E controller IP is targeting ~4 TB/s per-stack bandwidth. The EMC consequence is the interface itself: HBM4 widens the per-channel data path to a 2,048-bit interface, and even though per-pin signaling stays relatively modest (~8–10 GT/s), the aggregate simultaneous-switching current is enormous. That drives ground-bounce and a dense, broadband emission profile across the interposer. Shielding an HBM-class package is now a power-integrity problem as much as a field-containment problem — the return path is the design.

SiC — the bottleneck moved. The silicon-carbide power story changed character in 2025. The constraint is no longer the wafer. SiC wafer-fab utilization fell to roughly 50% in 2025 as substrate capacity caught up; the device lines downstream run nearer 70%. The real chokepoint is now packaging — sintered-silver die attach, the thermal interface, and the high-voltage isolation molding. Buy the package, not the die.

One Thing

For two decades the supply-chain default was: memory comes from Asia, and the only question is which Asian supplier. Micron's $50B says the default itself is now negotiable. The transition will take until 2028 to show up in lead times — but the procurement mindset should change today. Asia-default is a choice now, not a fact.

POCONS USA — EMI shields + components. San Diego, CA. Products manufactured in Korea (IATF 16949). — Mike Kwak, POCONS USA